1. Field of the Invention
The present invention relates to a method and apparatus for rapidly selecting types of buffers that are inserted into the clock tree and, more particularly, to a method and apparatus for rapidly selecting types of buffers that are inserted into the clock tree for high-speed very-large-scale-integration (VLSI).
2. Description of Related Art
The current high-speed VLSI usually uses the clock frequency as a target of the speed for data processing. The clock frequency is the frequency of the clock signal in the logic changing between 0 and 1. In a digital circuit, a clock net needs to transmit a clock signal from a dispatching point to a receiving point of any synchronous system of the digital circuit to make the synchronous systems synchronously operated under a timing design standard.
With reference to FIG. 1a that shows an inner structure of a simple IC wafer, the macro cells 14 in the wafer have finished floorplaning, and each cell has finished placement. The clock signal is transmitted from an exterior to an interior of the wafer via a pad 10 and to multiple pins of each of the macro cells 14 via a clock net 12. In each macro cell 14, the clock net 12 continually extends to each part of a subsidiary synchronous system.
In the process of transmitting signal, the signal integrity must be maintained as much as possible, that is, the clock delay and clock skew need to be possibly miniaturized. Shorteninig the clock delay can promote the speed of transmitting the clock signal. A signal error and a logical error may occur when the clock skew is over the standard value.
FIG. 1b is an exploded view of FIG. 1a. The input pad 10 of the clock signal is called a root. The received end of a flip-flop 16 is called a leaf. A complete path is formed to contain buffers and connecting circuits from the pad 10 (root) to the clock signal receiving end B1.1 (leaf) of the flip-flop 16. The accumulated delays of the buffers and the connecting circuits are called path delay. The path delays of two paths, respectively, connected to the roots (B1.1 and F 1.3) are one set of a clock skew. A buffer 18 is inserted to the clock net 12 for reducing time delay and the clock skew of each path of the clock tree.
FIG. 2 is an IC design flow chart of U.S. Pat. Nos. 5,564,022, 5,638,291 and 5,974,245. The conventional design usually processes placement 21 and coil 25. The current design adds the composing steps 22, 23 and 24 into the layout design. However, all the inserted buffers are in one type as shown in FIG. 2. The various buffers of the timing library are not considered. Consequently, the timing control of the clock tree net cannot fully satisfy the timing design standard.